1. Field of the Invention
This invention relates to a charge transfer device for use in, for example, a solid-state image sensor or a delay element, and a manufacturing process therefor.
2. Description of the Related Art
A conventional charge transfer device for use in, for example, a solid-state image sensor or a delay element is shown in FIGS. 6. FIGS. 6(a), 6(b), and 6(c) respectively are a schematic plan view, a schematic cross section taken on line VI(b)--VI(b) of FIG. 6(a), and a schematic cross section taken on line VI(c)-VI(c), which are disclosed in JP-A 57-7964.
In an n-type silicon substrate 1, there is a p-type well 2, in which there is an n-type well 3 in which a charge transfer channel is to be formed. There are n+ regions 4 containing an n-type dopant at a higher concentration than that in the n-type well 3, on both sides of the n-type well 3 along its charge transfer direction (the direction of line X-X' in the FIG.), and around the n+ region 4, a p+ channel stopper 7 is formed. On the n-type well 3 and the n+ region 4, there are a number of gate electrodes 6 via a gate insulator 5 consisting of, for example, an oxide film such as SiO.sub.2.
FIG. 7 shows an electric potential distribution along line Z-Z' of FIG. 6(c), i.e., the depth direction, where a lower position has a higher potential. In this figure, the origin of the depth direction is the silicon/gate insulator interface, and as a specific example, 0 V is applied to the p+ channel stopper 7 and the p-type well 2 and a lower(VL) or higher voltage(VH) to the gate electrode 6. To the n-type silicon substrate 1, a voltage with a reverse bias to the p-type well 2 is applied. The highest potential in the potential distribution along the depth direction shown in FIG. 7, is referred to as a "channel potential".
When a higher voltage(VH) is applied to a gate and a lower voltage(VL) is to two adjacent gates, electrons are transferred to beneath the gate electrode to which the VH is applied, causing a potential reduction. The potential may be reduced to the channel potential of the adjacent gate electrodes to which the VL is applied. The dotted line in this figure indicates the potential distribution at this time. An electric charge which may cause the potential change is the maximum transferable charge.
By reference to FIGS. 8(a), 8(b), and 8(c), a process for charge transfer in the charge transfer device shown in FIGS. 6(a)-6(c) will be described. FIG. 8(a) is the same schematic cross section as that shown in FIG. 6(b). FIG. 8(b) shows a channel potential distribution along line VIII(b)-VIII(b) of FIG. 8(a) at each time indicated in FIG. 8(c). FIG. 8(c) shows timing of a voltage pulse applied to the gate electrode of the charge transfer device. FIGS. 8(a) and 8(b) are depicted in a manner that they horizontally have the same position, and in FIG. 8(b) a lower position has a higher potential. To electrodes 4V1 to 4V4 is applied a binary pulse varying between the higher(VH) and the lower(VL) voltages as shown in FIG. 8(c).
The lower voltage is a voltage(pinning voltage) by which positive holes are stored in the silicon/oxide film interface to make the interface potential 0 V. In this manner, a dark current occurring via a silicon/oxide film interface level may be minimized.
The higher voltage is a voltage which is below the channel potential when the lower voltage is applied. Thus, a transferred charge does not reach the silicon/oxide film interface even when a maximum transferable charge (Qmax) is transferred, and is not trapped on the interface level. The charge can be, therefore, transferred without reduction of a transfer efficiency.
First, at time T1, the higher voltage (VH) is applied to .phi.V1 and .phi.V2 electrodes, and the channel potential increases beneath the electrodes, to cause charge storage. The stored charge is indicated by the slanted line in FIG. 8(b). At time T2, .phi.V3 is at the higher voltage (VH) while .phi.V1 at the lower voltage (VL), and thus, a charge is transferred to beneath the electrodes .phi.V2 and .phi.V3. In a similar manner, at T3 and T4, a charge is transferred to beneath electrodes .phi.V3 and .phi.V4 and electrodes .phi.V4 and .phi.V1, respectively. Then, at T5, a charge is transferred to beneath electrodes .phi.V1 and .phi.V2, returning to the state at T1 except that a charge is moved to the right, i.e., beneath the electrodes .phi.V1 and .phi.V2. By repeating the above process, a charge is sequentially transferred to the right direction. Such charge transfer is indicated by a right oblique downward arrow in FIG. 8(b).
Next, the reason why the maximum transferable charge (Qmax) is increased by the charge transfer device shown in FIGS. 6(a)-6(c), will be described. FIG. 9(a) is a cross section taken on line IX(a)-IX(a) of FIG. 6(a). FIG. 9(b) shows a channel potential distribution along line IX(b)-IX(b) of FIG. 9(a) when a lower (VL) or higher (VH) voltage is applied, where the dotted line indicates a distribution for a charge transfer device without an n+ region. FIG. 9(a) shows a capacity at the local maximum of the potential (channel position) in the n-type well 3 when a voltage VG is applied to the gate electrode. A capacity between the channel position and the gate electrode (Cs) is the sum of serial connection of the gate insulator capacity and the capacity in the silicon from the silicon/gate insulator interface to the channel position. A capacity of both sides (Ccs) is one between the channel position and the p+ channel stopper 7. A capacity below the channel position (Cb) is one between the channel position and the p-type well 2.
When a voltage VG is applied to the gate electrode and 0 V is to the p+ channel stopper 7 and the p-type well 2, relationship between a variation of the channel potential .DELTA..phi.ch and a variation of the gate voltage .DELTA.VG can be represented by the following equation: EQU .DELTA..phi.ch=.DELTA.VG.multidot.Cs/(Cs+2Ccs+Cb)
A charge stored beneath the gate electrode can be substantially represented by the following equation: ##EQU1##
A value obtained by integrating the above Equation (1) with the variation (amplitude) of the gate electrode is the maximum transferable charge (Qmax). It will be understood that when the amplitude is constant, a larger Cs gives a larger Qmax.
The solid line in FIG. 9(b) indicating the channel potential distribution along line V-V' when a lower (VL) or higher (VH) voltage is applied to the gate electrode, will be referred. The horizontal position is matched with the corresponding position in FIG. 9(a).
A concentration and a width in the n+ region 4 is adjusted so that when the lower voltage (VL) is applied, the curved channel potential line is changed within the n+ region 4 to be straight throughout the n-type well 3. When the higher voltage (VH) is applied, a depletion layer formed by p-n junction between the p+ channel stopper 7 and the n+ region 4 is extended to enter the n-type well 3. The straight part of the channel potential is, therefore, shorter than one when the lower voltage (VL) is applied. A capacity between the straight part of the channel potential and the gate electrode is Cs, which contributes a charge as indicated by Equation (1). On the other hand, the n+ region 4 forms p-n junction with the p+ channel stopper 7, and a potential increases from 0 V on the stopper side to .phi.ch. The capacity of this part is Ccs, which does not contribute charge according to Equation (1). Increase of the straight part of the channel potential, therefore, leads to increase of Qmax.
In FIG. 9(b), the dotted line indicates a channel potential distribution along line V-V' when without the n+ region 4, a lower (VL) or higher (VH) voltage is applied to the gate electrode. Since in this case, a concentration of the n-type dopant is lower than that in the n+ region, the curve of the channel potential is gentler around both ends, and thus the straight part of the channel potential is shorter.
As described above, increase of Qmax in the charge transfer device in FIGS. 6(a)-6(c) is owing to the fact that the device has the n+ region, leading to a steeper curve (rate of change) of the channel potential around both ends and increase in the straight part of the channel potential.
Next, a manufacturing process for the charge transfer device shown in FIGS. 6(a)-6(c) will be described. FIGS. 10(a)-10(d) are schematic cross-sectional process views, showing each manufacturing step with a cross section taken along line VI(c)-VI(c) of FIG. 6(a).
First, boron is ion-implanted with an energy of 150 to 200 kev and a dosage of 1 to 5.times.10.sup.12 /cm.sup.2 on the surface of an n-type of silicon substrate 1 having a phosphorous concentration of an order of 10.sup.14 /cm.sup.3 ; a p-type well 2 is formed by heating at 1200.degree. C. for 30 min to 2 hours; and then an oxide film 9 is formed by wet oxidation at 900.degree. C. for about 7 min. As shown in FIG. 10(a), on the film a photoresist 81 is formed with a thickness of about 2 .mu.m by a photolithography technique and then boron is ion-implanted with an energy of 20 to 40 keV and a dosage of 1 to 5.times.10.sup.13 /cm.sup.2, to form a p+ channel stopper 7.
Next, after removing the photoresist 81, a photoresist 82 with a thickness of about 2 .mu.m as shown in FIG. 10(b), and then phosphorous is ion-implanted with an energy of 70 to 150 keV and a dosage of 1 to 5.times.10.sup.12 /cm.sup.2, to form an n-type well 3.
Then, after removing the photoresist 82, photoresists 83a and 83b with a thickness of about 2 .mu.m are formed and ions are implanted to both sides of the n-type well 3, with the same energy as that for the above n-type well 3 and with a dosage 0.2 to 2 times as high as that for the n-type well 3, to form an n+ region 4.
Then, after removing the photoresist, the substrate is heated at 950 to 980.degree. C. for 30 min to 1 hour under an atmosphere of nitrogen, to activate the ion-implanted dopant, and then the oxide film 9 is wet-etched with hydrofluoric acid.
Then, as shown in FIG. 10(d), a gate insulator 5 is formed by wet oxidation at 900 to 980.degree. C. for 5 to 30 min, on which a polysilicon gate electrode 6 doped with a dopant by lithography and etching, to provide a charge transfer device as shown in FIGS. 6(a)-6(c).
However, if the conventional charge transfer device as shown in FIGS. 6(a)-6(c) is prepared by the above manufacturing process as shown in FIGS. 10(a)-10(d), reduction in the width of the n-type well gives the narrower photoresist 83a in FIG. 10(c), causing peeling or falling of the photoresist. As an example in which the problem may be prominent, an interlined type of two-dimensional CCD image sensor will be described.
FIG. 11 schematically shows an interline type of CCD image sensor. Adjacent to each photodiode array which is two-dimensionally aligned, a vertical CCD 12 is formed, which is connected with the photodiodes 10 via transfer gates 11. There are provided p+ channel stoppers 15, for example, between photodiodes 10, between a photodiode 10 and the vertical CCD 12 as well as between a photodiode 10 and horizontal CCD 13. The lower end of each vertical CCD 12 is connected with the horizontal CCD 13, an end of which is connected with an amplifier 14. A signal charge which has been obtained by photo electric conversion is read out to the vertical CCD 12 via the transfer gates 11, then transferred at the vertical CCD 12 and the horizontal CCD 13, and then amplified by the amplifier 14 to be output. The region enclosed by the dotted line in the figure is a unit pixel 16, whose size has been recently reduced as a two-dimensional CCD image sensor has have a reduced size of chip and more pixels.
However, it is desirable to increase the area of the photodiode 10 as much as possible for ensuring a certain sensitivity or capacity of the photodiode. To this end, it is desired that a transfer charge per a unit area of the vertical CCD 12 is increased to reduce the area of the vertical CCD 12.
If the charge transfer device shown in FIGS. 6(a)-6(c) is applied to a vertical CCD for solving the problem, there may be difficulty in the above manufacturing process as shown in FIGS. 10(a)-10(d), due to the fact that as the n-type well 3 becomes narrower, the photoresist 83a becomes narrower. In an interline type of two-dimensional CCD image sensor, a pixel has been gradually miniaturized and the minimum pixel reported to date corresponds to a square whose sides have a length of about 4 to 5 .mu.m. In the sensor, the vertical CCD has a width of below 1.5 .mu.m, which is the distance between the p+ channel stoppers 7 in FIGS. 10(a)-10(d). An opening of the photoresist shown in FIG. 10(c) whose minimum design dimension is 0.5 .mu.m, has a dimension of 0.5 .mu.m, and the width of the photoresist 83a is below 0.5 .mu.m. In an optical format of 1/2 inch, the length of the vertical CCD is below about 5 mm, and therefore, the photoresist 83a is stripe-shaped with a width of below 0.5 .mu.m and a length of 5 mm. Such a shape is likely to cause peeling or falling due to inadequate adhesion of the photoresist, which may be prominent when the width of the vertical CCD is further reduced. Because of the above problems, it has been very difficult to prepare a charge transfer device whose vertical CCD width is below 1.5 .mu.m, in the shape shown in FIGS. 6(a)-6(c), according to the process of the prior art.